1. Field of the Invention
This invention relates to the field of electronic connectors, and in particular, to a structure and method of electrically interconnecting two electronic modules having differing conductive array parameters, wherein an interposer spatially transforms such differing conductive array parameters.
2. Description of Related Art
In surface mount technology, integrated circuits (ICs) have leads, or signal Input/Output (I/O) connections, and Power/Ground (P/G) connections which are connected to ceramics or organic packages which in turn have leads extending therefrom for connection to a printed circuit board having a corresponding set of I/O connections. Such IC assemblies include, for example, single chip modules (SCM), wherein one chip is connected to a single chip module, or multi-chip module (MCM), wherein more than chip is connected to an organic or ceramic package containing multi-layers of thick-film or thin-film circuitry separated by dielectric layers and interconnected by vias. The electrical attachment of the IC to the package resulting in an IC package is often referred to as the first level of attachment. In this attachment level, P/G and I/O connections exist on surfaces of both IC dies and first level packaging. Such connections terminate in conductive pads or fingers which are used to connect both components using solder balls (C4), or wirebonds. The resultant assembly is often referred to as an IC package.
The electrical attachment of the IC package to the board is the second level of attachment. In second level attaching, I/O connections exist on surfaces of both IC packages and circuit boards. Such connections terminate in conductive leads, pins, wires, pads, balls, fingers, and any other mating system known in the art, thereby connecting the IC package to a circuit board for receiving, generating or continuing an electrical interconnection. Typically, the second level electrical attachment of two electronic modules using the above connection terminals is achieved by a variety of methods as disclosed in the prior art, such as wire bonding, Pin Grid Arrays (PGAs), Ball Grid Arrays (BGAs), Column Grid Arrays (CGAs), coaxial interconnect devices, elastomeric interconnect devices, and the like. A variety of such prior art discloses not only connecting the IC package to the board, but also assisting in the absorption of the difference in Coefficient of Thermal Expansion (CTE) between the package and the circuit board. However, even with such disclosed attachment means, a large CTE mismatch can still cause failure at various sites in the attachment when the first level packaging is made from a ceramic or metal composite.
The use of interposers is known and used in the art to interconnect two substrates, thereby providing an electrical interconnection between such substrates. For example, the prior art discloses the use of interposers in a first level attachment between an IC and an electronic package module. An interposer generally comprises an insulating layer and a plurality of column-like electrical conductors disposed through the insulating layer, wherein the insulating layer protects the conductive arrays. The column-like conductors have two ends for attaching to conductive arrays. Therein, the ends of the column-like conductors provide electrical connections between corresponding conductive arrays of two electronic modules on opposite sides of the interposer. When the corresponding conductive arrays have differing pitch, the interposer will typically include one or more x-y redistribution layers internally to provide the required x-y transformation function. Generally, it is difficult to provide an array of interconnecting signal lines with tightly controlled line impedence capable of operating with low noise at high frequency, such as above 500 MHz.
As disclosed in the prior art, interposers may comprise a material with the same CTE as the conductive arrays, thereby favorably altering the stress and/or strain distribution between two electronic modules. In such disclosures as electrical currents heat up the electronic module the conductive arrays will not stress as severely as they would if they were directly bonded to a material that had a substantially different CTE. Alternatively, the interposer may be comprised of a material with a CTE that is intermediate in value between that of the IC package and the board such that the strain associated with the lateral displacement of the IC package and the board is spread out over two sets of conductive arrays on the top and bottom of the interposer structure. While interposers have been disclosed in the prior art in both first and second level attachments, there is no known interposer for a first or second level attachment of two electronic modules having the same number of arrays in corresponding array grids but differing parameters of such conductive arrays, such as pitch, size, shape, array type, and combinations thereof, and without at least one such x-y redistribution layer.
Currently, the trend for IC chips is to increase the density and number of I/O connectors on a die, thereby increasing the number of I/O connections at both first and second level attachments. Such trends furthermore result in IC packages and boards with conductive connector arrays of different size, shape, pitch, and connector type. Since the board fabrication technology can not easily increase the I/O array density, any increase in I/O count is accommodated by an increase in the dimensions of the I/O connector array of the board required to interconnect in a second level attachment, the first level package is then used to transform the high density I/O connection of the IC into the low density I/O connection of the board. In parallel, the first level package can accommodate an increase in I/O count by increasing the number of x-y redistribution layers in the package, and by increasing its size to match the increased dimensions of the I/O connection array on the board. When the first level package CTE is different than the CTE of the second level package, any increase in the size of the first level package size will result in an increased mechanical stress level of the assembly, consequently resulting in decreased product reliability. The above methods of attaching two electronic modules having differing array size, shape, pitch, and the like, with increased I/O count, leads to increased production costs, increased size of the resulting second level attachment, and decreased reliability.
As the trends continue for IC packages having increased density, number of ICs on a package, increased number of I/O connections at the first and second level of attachment, and differing I/O conductive connection array size, shape, pitch, connector type, and the like, the demand continues for improvements in connecting electronic modules in surface mount technology. An ideal first or second level connection scheme is an interconnect structure that would provide the ability to directly connect two electronic modules having differing I/O conductive connector array parameters such as size, shape, pitch, and connector type, be compatible with the fabrication for a variety of conductive arrays, have a simple mechanical structure such that it can be easily and inexpensively manufactured, have a high processing yield, produce a decrease in the size of the resultant surface mount package, and be consistently reliable. Furthermore, such an interconnect structure would allow for high density I/O connections, controlled impedence, high signal isolation, and high reliability.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method of making an improved interconnection structure which attaches two electronic modules at a first and/or second level attachment.
It is another object of the present invention to provide an improved interconnection structure with tightly controlled line impedance capable of operating with low noise at high frequency.
A further object of the invention is to provide an improved interconnection structure which attaches two electronic modules having differing I/O array parameters.
It is yet another object of the present invention to provide an improved interconnection structure which allows for high density I/O connections.
Another object of the invention is to provide an improved interconnection structure which allows for improved, high signal isolation.
Another object of the invention is to provide an improved interconnection structure which produces a decrease in the size of the resultant surface mount package.
It is yet another object of the present invention to provide an improved interconnection structure which decreases production costs at the second level attachment.
Another object of the invention is to provide x-y translation without the use of x-y redistribution layers.
Still another object of the invention is to provide an improved interconnection structure having increased yield and reliability.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.